1. Field of the Invention
The present invention relates to a logic simulation system, more particularly, to a logic simulation system which adopts a constitution that simulates logic circuits to thereby display the logic simulation result information on a display.
In recent years, with respect to logic circuits provided in a computer system, or the like, high degree of integration thereof has been increasingly developed. With the development, time required for an analysis of the logic circuits has been prolonged. In view of the fact, it has been demanded to realize a logic simulation system by which it is possible to simply carry out a verification of the operation of designed logic circuits and an analysis of erroneous operation thereof.
2. Description of the Related Art
A conventional logic simulation system has adopted a constitution which displays logic simulation result information on a display according to a free-format display format, or a constitution which displays logic simulation result information on a display according to a stream display format.
Namely, there has been adopted a free-format display format in which logic simulation result information at designated times are displayed according to a user-defined display format, or a stream display format in which logic simulation result information at signal terminals are displayed in the form along the passage of time.
However, both of the display formats have a merit and a demerit, respectively, as described below.
A constitution which displays logic simulation result information according to the free-format display format has an advantage in that signal values for signal terminals constituting the logic simulation result information can be displayed in great numbers on a display. However, it is impossible to grasp the flow of time with respect to the signal values, and thus a problem occurs in that, when an error is found in logic circuits, it takes a long time to analyze a cause for the error.
On the other hand, a constitution which displays logic simulation result information according to the stream display format has an advantage in that, when an error is found in logic circuits, it is possible to easily analyze a cause for the error. This is because time-series data of the signal values for signal terminals are displayed. However, due to the display of the time-series data, the number of signal terminals which can be displayed at one time on a display is relatively decreased. As a result, a problem occurs in that it is necessary to troublesomely repeat a display for another image plane, and thus it takes a long time to analyze the logic circuits.